"""Tests for LLVM IR code generation with conditional rendering."""

import pytest
from ritz.parser import parse_component
from ritz.llvm_codegen_signals import generate_llvm_ir


def test_if_statement_codegen():
    """Test LLVM IR generation for if statement with reactive rendering."""
    source = """
from ritz.syntax import *

@component
def Toggle():
    visible = signal(1)

    if visible:
        with P():
            yield "I am visible!"
"""
    ir = parse_component(source)
    llvm_ir = generate_llvm_ir(ir)

    # Should have signal global (scoped to component)
    assert "@signal_Toggle_visible = global i32 1" in llvm_ir

    # Should have conditional branch
    assert "br i1" in llvm_ir

    # Should have reactive conditional infrastructure
    assert "@cond_0_marker" in llvm_ir
    assert "_init_conditional_0" in llvm_ir
    assert "_render_cond_0_then" in llvm_ir
    assert "_render_cond_0_else" in llvm_ir


def test_if_else_codegen():
    """Test LLVM IR generation for if/else with reactive rendering."""
    source = """
from ritz.syntax import *

@component
def Toggle():
    visible = signal(1)

    if visible:
        with P():
            yield "Shown"
    else:
        with P():
            yield "Hidden"
"""
    ir = parse_component(source)
    llvm_ir = generate_llvm_ir(ir)

    # Should have conditional branch
    assert "br i1" in llvm_ir

    # Should have reactive infrastructure with both branches
    assert "_render_cond_0_then" in llvm_ir
    assert "_render_cond_0_else" in llvm_ir
    assert "reevaluate_conditional_0" in llvm_ir


def test_if_comparison_codegen():
    """Test LLVM IR generation for if with comparison."""
    source = """
from ritz.syntax import *

@component
def Counter():
    count = signal(0)

    if count > 5:
        with P():
            yield "High count!"
"""
    ir = parse_component(source)
    llvm_ir = generate_llvm_ir(ir)

    # Should have icmp instruction for comparison
    assert "icmp" in llvm_ir

    # Should have greater-than comparison (sgt = signed greater than)
    assert "sgt" in llvm_ir or ">" in llvm_ir