Add basic component composition support

- Handle yield_component statement type
- Call child component render function
- Enables: yield VerticalTabs()
- All tests passing (30/30)
- Tabs.wasm size: 3185 → 3205 bytes

ritz/llvm_codegen_signals.py

@@ -223,6 +223,8 @@ class SignalLLVMIRGenerator:
             return self._emit_with(stmt)
         elif stmt["type"] == "yield":
             return self._emit_yield(stmt)
+        elif stmt["type"] == "yield_component":
+            return self._emit_yield_component(stmt)
         elif stmt["type"] == "if":
             return self._emit_if(stmt)
         elif stmt["type"] == "match":
@@ -269,6 +271,16 @@ class SignalLLVMIRGenerator:
 
         return None
 
+    def _emit_yield_component(self, stmt: dict[str, Any]) -> str | None:
+        """Emit a component instantiation (yield SomeComponent(...))."""
+        component_name = stmt["component"]
+
+        # For now, just call the render function
+        # TODO: Pass arguments when component parameters are supported
+        self.lines.append(f"  call void @render_{component_name}()")
+
+        return None
+
     def _emit_match(self, stmt: dict[str, Any]) -> str | None:
         """Emit a match/case statement using LLVM switch."""
         # Generate unique labels