From 0063a8536c3bb01404aa88098c77810dd36e7202 Mon Sep 17 00:00:00 2001
From: Aaron Sinclair <aaron.sinclair@bettercomp.com>
Date: Sat, 15 Nov 2025 03:29:57 -0800
Subject: [PATCH] Add comparison operator support for if conditions

- Extend _emit_expr() to handle 'compare' type expressions
- Map Python comparison ops (Gt, Lt, Eq, etc) to LLVM icmp predicates
- Convert i1 result to i32 for compatibility
- All conditional tests passing (3/3)
---
 .../llvm_codegen_signals.cpython-313.pyc      | Bin 20618 -> 21423 bytes
 ritz/llvm_codegen_signals.py                  |  23 ++++++++++++++++++
 2 files changed, 23 insertions(+)

diff --git a/ritz/__pycache__/llvm_codegen_signals.cpython-313.pyc b/ritz/__pycache__/llvm_codegen_signals.cpython-313.pyc
index db4317ae62bbfcd1a1fc6d4eefc94c217ac799b9..435bdd9ff92abb3f97211fca4e634d64f5d10b99 100644
GIT binary patch
delta 996
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delta 379
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diff --git a/ritz/llvm_codegen_signals.py b/ritz/llvm_codegen_signals.py
index 46d640f..3f89362 100644
--- a/ritz/llvm_codegen_signals.py
+++ b/ritz/llvm_codegen_signals.py
@@ -247,6 +247,29 @@ class SignalLLVMIRGenerator:
         elif expr["type"] == "constant":
             # Return constant inline
             return str(expr["value"])
+        elif expr["type"] == "compare":
+            # Handle comparison (e.g., count > 5)
+            left_var = self._emit_expr(expr["left"])
+            right_var = self._emit_expr(expr["comparators"][0])
+
+            # Map Python comparison ops to LLVM icmp predicates
+            op_map = {
+                "Gt": "sgt",    # signed greater than
+                "Lt": "slt",    # signed less than
+                "GtE": "sge",   # signed greater or equal
+                "LtE": "sle",   # signed less or equal
+                "Eq": "eq",     # equal
+                "NotEq": "ne",  # not equal
+            }
+
+            icmp_op = op_map.get(expr["op"], "eq")
+            result_var = self._new_var()
+            self.lines.append(f"  %{result_var} = icmp {icmp_op} i32 %{left_var}, {right_var}")
+
+            # Convert i1 to i32 for compatibility
+            result_i32 = self._new_var()
+            self.lines.append(f"  %{result_i32} = zext i1 %{result_var} to i32")
+            return result_i32
         else:
             # Unknown expression type
             return "0"